1. Field of Invention
The present invention generally relates to a delay line circuit, a delay locked loop and a tester system, and more particularly, to the frequency adjustable delay line circuit, the delay locked loop, and the tester system including the same.
2. Description of Prior Art
For the operation of a DDR SDRAM (double data rate synchronous DRAM), a plurality of reference clock signals with a same frequency but different phases are used. A delay locked loop (DLL) is used to lock the input reference clock signal and to generate a plurality of output clock signals with different phases from that of the input reference clock signal.
In many applications, the delay locked loop is used for maintaining the duty cycle of the clock signal outputted by the delay locked loop at a preset value (i.e. fifty percent duty cycle) based on its characteristic.
However, the conventional delay locked loop can't change the frequency of the output clock signal. If designers want to apply frequency multiplying function and duty cycle maintaining function in a single IC design simultaneously, the phase locked loop must be added in to provide the frequency multiplying function. In this way, the chip size may increase and the clock signals between the delay locked loop and the phase locked loop also may interfere with each other to lead the performance of the circuit being affected.